The present invention relates to a digital-to-analog converter (hereinafter, referred to as "DAC") utilizing a sigma-delta modulator or .SIGMA..DELTA. modulator, and more specifically relates to a circuit construction thereof for reducing a noise during a silent period in which no signal is inputted into the DAC.
Recently in the field of digital audio technology, there has been utilized a one bit DAC provided with a .SIGMA..DELTA. modulator operative to effect sigma-delta modulation to requantize a multi-bit digital signal into a single bit digital signal. As known in the field, the .SIGMA..DELTA. modulator is a sophisticated modification of a .DELTA. modulator, substantially including an integrator disposed at an input stage of the .DELTA. modulator for low frequency boost and a differentiator disposed at an output stage of the .DELTA. modulator for low frequency cut, thereby performing noise-shaping effective to distribute quantization noise in a higher frequency range to reduce S/N ratio in a lower or audio frequency range.
FIG. 7 is a block diagram showing a typical construction of the .SIGMA..DELTA. modulator of dauble loop type. The .SIGMA..DELTA. modulator operates such that a multi-bit input data D.sub.i of, for example, 16-bit length is inputted into an adder 71 which calculates a difference between the input data D.sub.i and a negative feedback data a which is obtained by delaying an output from a one bit quantizing unit 75 through a one sample delay circuit 76. This differential signal b is integrated by a first integrator 72. An output c of the integrator 72 is inputted into another adder 73 which calculates a difference between the output c and the before-mentioned negative feedback signal a. An output d of the adder 73 is integrated by a second integrator 74. An output e of the integrator 74 is inputted into the before-mentioned one bit quantizing unit 75. The quantizing unit 75 is comprised of a zero cross comparator operative when a value of the output e of the second integrator 74 is positive or zero to produce a onebit output data D.sub.o indicative of quantization "+1", and otherwise operative when a value of the output e of the second integrator 74 is negative to produce a onebit output data D.sub.o indicative of quantization "-1". As described before, the output data D.sub.o is negatively fed back through the one sample delay circuit 76, in the form of the feedback data a, to the respective adders 71 and 73.
In the thus constructed .SIGMA..DELTA. modulator, if a multi-bit data D.sub.i indicative of value "0.6" is inputted every sample timing, the above mentioned various data or signals a, b, c, d and e take variable values as indicted in the following table 1.
TABLE 1 ______________________________________ D.sub.i a b c d e D.sub.o ______________________________________ 0.6 * * 0 * 0 +1 0.6 +1 -0.4 -0.4 -1.4 -1.4 -1 0.6 -1 1.6 1.2 2.2 0.8 +1 0.6 +1 -0.4 0.8 -0.2 0.6 +1 0.6 +1 -0.4 0.4 -0.6 0 +1 0.6 +1 -0.4 0 -1.0 -1.0 -1 0.6 -1 1.6 1.6 0.6 0.4 +1 0.6 +1 -0.4 1.2 0.2 0.6 +1 0.6 +1 -0.4 0.8 -0.2 0.4 +1 0.6 +1 -0.4 0.4 -0.6 -0.2 -1 0.6 -1 1.6 2.0 3.0 2.8 +1 0.6 +1 -0.4 1.6 0.6 3.4 +1 0.6 +1 -0.4 1.2 0.2 3.6 +1 0.6 +1 -0.4 0.8 -0.2 3.4 +1 0.6 +1 -0.4 0.4 -0.6 2.8 +1 0.6 +1 -0.4 0 -1.0 1.8 +1 0.6 +1 -0.4 -0.4 -1.4 0.6 +1 0.6 +1 -0.4 -0.8 -1.8 -1.2 -1 0.6 -1 1.6 0.8 1.8 0.6 +1 0.6 +1 -0.4 0.4 -0.6 0 +1 ______________________________________
In this table 1, there are obtained twenty number of singlebit output data D.sub.o containing sixteen number of quantizations "+1" and four number of quantizations "-1". Therefore, when filtering these sequential output data D.sub.o through an analog low pass filter (not shown in FIG. 7) to produce an analog output signal, this analog output signal may have an averaged level calculated according to the following relation (1): EQU (16-4)/20=0.6 (1)
In the above one bit DAC utilizing the .SIGMA..DELTA. modulator, since the feedback data a from the delay circuit 76 takes either value of quantization "+1" and "-1", the adder 71 will produce an output b having a value of "+1" or "-1" when the multi-bit input data D.sub.o becomes zero, for example, during a silent period of a given audio signal. Therefore, if the integrator 72 has stored therein a last internal data having a value other than an integer before the silent period, the integrator 72 produces an output c which may oscillate between positive and negative values around an offset level deviated from the zero level during the silent period. When the output c of the first integrator 72 contains such offset, the second integrator 74 accumulates the offset value so that its output e abruptly shifts periodically everywhen the accumulated value exceeds a critical level. Therefore, the output e of the subsequent integrator 74 is not stabilized to thereby produce noise at a particular frequency of the audio range corresponding to the shifting period.
In view of this drawback, there have been conventionally proposed various counter measures such as the muting method and the resetting method in order to reduce noise during a silent period. The muting method is such that an output of an analog circuit subsequent to the DAC is muted upon detection of a silent period. The resetting method is such that an output of the integrator in the DAC is forcibly reset to the zero level upon detection of a silent period.
However, with regard to the muting method, a muting circuit must be added externally, thereby causing drawbacks such as the overall circuit construction is complicated and a top part of a following audio signal is missing due to a response delay of the analog circuit after releasing the muting operation.
With regard to the resetting method, an output of the integrator abruptly varies at the time of resetting to thereby cause a drawback that the analog output may produce an irregular click sound.